The present invention relates to a video chroma signal processing circuit in an equipment operating with video signals such as a television receiver and a video cassette recorder (VCR), and more particularly to a video chroma signal processing circuit which reproduces a video signal having a frequency higher than the frequency (the frequency limited by what is called the sampling theorem) which is one half of a sampling clock frequency of an AD converter.
Digital equipments operating with video signals have been in progress of late years. Such a trend has also extended to television receives, VCRs and the like which are public equipments. This is a technique expected much by which not only reduction by the quantity of components and improvement of reliability are expected, but also development to EDTV becomes easier for a video chroma signal processing circuit by means of digital techniques.
In video chroma signal processing digital circuits, a frequency characteristic of a luminance signal is limited to one half of a sampling clock of an AD converter by what is called the sampling theorem. A frequency which is used frequently as a sampling clock of an AD converter is at 14.31818 MHz which is four times as high as a subcarrier frequency. In this case, the maximum frequency which passes through reaches approximately 7.1 MHz, which produces approximately 570 lines if computed in terms of horizontal resolution. On the other hand, the horizontal resolution at 700 lines to 750 lines are required as the performance demanded for a high grade television receiver in the domestic market. Therefore, it is impossible to reproduce the horizontal resolution demanded in the market in general with a conventional sampling frequency at 14.31818 MHz.
An example of an above-described conventional video chroma signal processing circuit applied with digital signal processing will be described hereinafter.
FIG. 1 shows a block diagram of an example of a conventional video chroma signal processing circuit applied with digital signal processing. In FIG. 1, a reference numeral 21 denotes a first AD converter which receives an analog composite video signal and converts that signal into a digital code. 22 denotes a second AD converter which receives a chroma signal separated from a luminance signal when inputted and converts the chroma signal into a digital code. 23 denotes a luminance signal processing circuit which receives the output signal of the first AD converter 22 and performs appropriate luminance signal processing such as contrast adjustment and contour correction. 24 denotes a first DA converter which receives the output signal of the luminance signal processing circuit 23 and converts a digital code into an analog signal. 25 denotes a multiplexer circuit which receives the output signal of the first AD converter 21 and the output signal of the second AD converter 22 and outputs the output signal of the first AD converter 21 at time of composite video signal demodulation and outputs the output signal of the second AD converter 22 when the analog luminance signal and the analog chroma signal are inputted after being separated from each other depending on a change-over signal a, 26 denotes a chrominance signal processing circuit which receives the output signal of the multiplexer circuit 25 and converts the chroma signal into primary color signals of an R-Y signal and a B-Y signal, and 27 and 28 denote a second DA converter and a third DA converter which receive the output signal of the chrominance signal processing circuit 26 and convert primary color signals of the R-Y signal and the B-Y signal in digital code into analog signals, respectively.
The operation of a video chroma signal processing circuit constructed as above will be described hereinafter.
First, an analog composite video signal or a luminance signal is inputted to the first AD converter 21 and converted into a digital code. The second AD converter 22 receives a chroma signal and converts it into a digital code. The luminance signal processing circuit 23 receives the output signal of the first AD converter 21 and performs appropriate luminance signal processing such as contrast adjustment and contour correction. The first DA converter 24 receives the output signal of the luminance signal processing circuit 23 and converts the digital code into an analog signal. As a result, an analog luminance signal is obtained as the output signal of the first DA converter 24. Further, the chrominance signal is reproduced as follows. The multiplexer circuit 25 receives the output signal of the first AD converter 21 and the output signal of the second AD converter 22, and then outputs the output signal of the first AD converter 21 at time of composite video signal demodulation and outputs the output signal of the second AD converter 22 when the luminance signal and the chrominance signal are inputted after being separated from each other in advance depending on the change-over signal a. The chrominance signal processing circuit 26 receives the output signal of the multiplexer circuit 25 and converts the chroma signal into primary color signals of an R-Y signal and a B-Y signal. The second DA converter 27 and the third DA converter 28 receive the output signals of the chrominance signal processing circuit 26 and convert primary color signals of the R-Y signal and the B-Y signal in digital code into analog signals, respectively.
In above-described construction, however, the signal frequency is limited to a band of approximately 7.1 MHz by the sampling theorem when 14.31818 MHz which is used frequently is adopted as a sampling frequency. This produces approximately 570 lines when computed in terms of the horizontal resolution. It is only required to raise the sampling frequency for obtaining a band wider than the above, but it is practically difficult to manufacture an AD converter of high accuracy at a frequency higher than the above, thus causing such problems that reproduction of a chrominance signal becomes complicated and the cost is also increased.